1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to an SRAM powered from two systems, including a logic-use power source and a memory cell-use power source.
2. Description of the Related Art
LSIs used in mobile instruments are required to reduce power consumption for achieving a longer drive time with a battery. Power consumption can be effectively reduced by lowering the supply voltage though the increase in characteristic variation among elements due to the recent progression of scaling results in a reduced operation margin of an SRAM used in the LSI, which makes it difficult to lower the operation voltage of the SRAM. In this case, the supply voltage to the entire LSI can not be lowered as a problem.
To address such the problem, a method for supplying a higher supply voltage than a logic-use supply voltage only to memory cells has been used (Non-Patent Document 1: J. Pille, et al., 2007 IEEE International Solid-State Circuits Conference Digest of Technical Papers, p322). In this case, it is possible to lower the logic-use supply voltage down to or lower than the operation voltage of the SRAM and accordingly suppress the power consumption in the LSI.
A further progression of device scaling, however, increasingly enlarges the estrangement between the memory cell-use power source and the logic-use power source. A rise in the memory cell-use supply voltage increases the current consumption in the memory cell-use power source. Accordingly, even a lowered logic-use supply voltage can not suppress the current consumption in the entire LSI sufficiently. The applicable supply voltage has an upper limit because of the reliability of the device. Accordingly, even the use of the memory cell-use power source can not ensure a sufficient operation margin.